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Exciting, Disruptive, Game-Changing RFSoCs from Xilinx

author:  Pageviews:347  release time:2018-07-31

RFSoCs are applicable to a wide variety of applications, from 5G mobile networks to radar, telecommunications, and electronic warfare.

Not since I got my hands on an UltraZed System-On-Module (SOM) containing a Xilinx Zynq UltraScale+ Zynq Multi-Processor System-on-Chip (MPSoC) a few weeks ago, have I been this excited.
No, I am not referring to Max's column on what my wife and I should name our forthcoming first-born child (see What's a Good Name for a Future Engineer?), but rather to the recent announcement by Xilinx of its new Radio Frequency SoC (RFSoC).
This All Programmable RFSoC combines the MPSoC and its associated programmable fabric with eight RF DACs and ADCs, all on the same piece of 16nm silicon, thereby allowing for some very exciting system solutions. These devices will find a ready home across a variety of applications, from upcoming 5G mobile networks to radar, telecommunications, and electronic warfare (EW), where EW includes things like characterizing and jamming electronic emissions.
The ADCs are sampled at 4 Gsps (gigasamples per second), while the DACs are sampled at 6.4 Gsps, all of which provides the ability to work across a very wide frequency range. The main benefit of this, of course, is a much simpler RF front end, which reduces not only PCB footprint and the BOM cost but -- more crucially -- the development time taken to implement a new system.
Speaking as a designer who has implemented FPGA-based systems utilizing both ultra-wideband (UWB) ADCs and DACs for space and military applications, to my mind these devices offer many advantages beyond the simpler RF front end and reduced system power that comes from such a tightly-coupled solution.
These devices also bring with them a simpler clocking scheme, both at the device-level and the system-level, ensuring clock distribution while maintaining low phase noise / jitter between the reference clock and the ADCs and DACs, which can be a significant challenge. If done wrong, this can result in a significant impact on system performance. From the technical white papers accompanying the RFSoC announcement, it appears that clock distribution was one of the prime considerations for the creators of these devices.
These RFSoCs will also simplify the PCB layout and stack, removing the need for careful segregation of high-speed digital signals from the very sensitive RF front-end. Of course, it would be foolish to think that these devices will not be accompanied with stringent routing guidelines in order to achieve the best performance, but the intermediate routing stage between the convertor and FPGA has been eliminated.
Combining the RF front-end with the MPSoC architecture -- which contains dual or quad-core 64-bit ARM Cortex-A53 processors and dual-core 32-bit ARM Cortex-R5 processors along with supporting peripherals and programmable fabric -- facilitates optimal system solutions. System designers can leverage the programmable logic to implement high-speed signal processing pipeline(s), while the processor cores can provide supervision and control, analytics, and dynamic configuration of the signal processing pipeline as required.
These devices confirm my belief about the need for a new paradigm in developing applications for programmable logic to ensure the provided capability can be fully exploited within a reasonable timeframe. Leveraging the capability of these devices is going to require the use of increased abstraction levels, such as high-level synthesis (HLS), a software-defined SoC (SDSoC) development environment, and third-party system tools -- not just traditional hand-coded Verilog and/or VHDL.
I am sure that more information on these devices will become available over the next few months. I, for one, am very excited to learn more about RFSoCs and I cannot wait to get my hands on one.

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